Improved Audible Noise Performance? Soft Start on Overvoltage? Integrated Brownout? Improved Light-Load Efficiency? Improved Transient Response? Complete System-Level Protection?
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Improved Audible Noise Performance? Soft Start on Overvoltage? Integrated Brownout? Improved Light-Load Efficiency? Improved Transient Response? Complete System-Level Protection? D to A Set Top Boxes? DLP is a trademark of Texas Instruments. Products conform to specifications per the terms of the Texas Instruments standard warranty.
Production processing does not necessarily include testing of all parameters. Ordering Information 2? Electrical Characteristics 4? Device Information 7? Functional Block Diagram 9? Typical Characteristics 10?
Application Information 16? Design Example 22? Additional References 29 DESCRIPTION Optimized for consumer applications concerned with audible noise elimination, this solution extends the advantages of transition mode—high efficiency with low-cost components—to higher power ratings than previously possible.
By utilizing a Natural Interleaving technique, both channels operate as masters that is, there is no slave channel synchronized to the same frequency. This approach delivers inherently strong matching, faster responses, and ensures that each channel operates in transition mode. Complete system-level protections feature input brownout, output over-voltage, open-loop, overload, soft-start, phase-fail detection, and thermal shutdown.
The additional FailSafe over-voltage protection OVP feature protects against shorts to an intermediate voltage that, if undetected, could lead to catastrophic device failure. This integrated circuit can be damaged by ESD. Texas Instruments recommends that all integrated circuits be handled with appropriate precautions. Failure to observe proper handling and installation procedures can cause damage. ESD damage can range from subtle performance degradation to complete device failure.
Precision integrated circuits may be more susceptible to damage because very small parametric changes could cause the device not to meet its published specifications.
These are stress ratings only and functional operation of the device at these or any other condition beyond those included under recommended operating conditions is not implied. Exposure to absolute-maximum-rated conditions for extended periods of time may affect device reliability.
VCC may exceed the absolute maximum input voltage if the source is current limited below the absolute maximum continuous VCC input current level. However, a small series resistor may be required to damp ringing due to stray inductance. See Figure 12 and Figure 13 for details. Thermal resistance is a strong function of board construction and layout. Air flow will reduce thermal resistance. S —? This clamp does not protect the device from an unregulated supply. A ms 2 Refer to Figure 12, Figure 13, Figure 14, and Figure 15 in the Typical Characteristics for typical gate drive waveforms.
The on-time proportionality factor, KT, is different in two-phase and single-phase modes. Device performance above the normal operating temperature is not specified or assured. Connect the analog and power grounds at a single point to isolate high-current noise signals of the power components from interference with the low-current analog circuits.
Error amplifier output: The error amplifier is a transconductance amplifier, so this output is a high-impedance current source. Connect voltage regulation loop compensation components from this pin to AGND. The on-time seen at the gate drive outputs is proportional to the voltage at this pin minus O an offset of approximately mV. During soft-start events undervoltage, brownout, disable or output over voltage , COMP is pulled low.
Normal operation only resumes after the soft-start event clears and COMP has been discharged below 0. Current sense input: Connect the current sense resistor and the negative terminal of the diode bridge to this pin. Connect the return of the current sense resistor to the AGND pin with a separate trace.
As input current increases, the voltage on CS goes more negative. This cycle-by-cycle over-current protection limits input current by turning off both gate driver GDx outputs when CS is more negative than the CS rising threshold approximately — mV. Current sense is blanked for approximately ns following the falling edge of either GD output. This blanking filters noise that occurs when current switches from a power FET to a boost diode.
In most cases, no additional current sense filtering is required. If filtering is required, the filter series resistance must be under ? To prevent excessive negative voltage on the CS pin during inrush conditions, connect the current sensing resistor to the CS pin through a low value external resistor.
O Channel A and channel B gate drive output: Connect these pins to the gate of the power FET for each phase through the shortest connection practical.
If it is necessary to use a trace longer than 0. This ringing can be reduced by adding a 5-? Using two pins to monitor for over-voltage provides redundant protection and fault tolerance.
The commanded on-time for channel A is immediately doubled when channel B is disabled, which helps to keep COMP voltage I constant during the phase management transient. PHB can also be driven by external logic signals to allow customized phase management. I Timing set: PWM on-time programming input. Bias supply input: Connect this pin to a controlled bias supply of between 14 V and 21 V. Also connect — a 0. F ceramic bypass capacitor from this pin to PGND with the shortest possible board trace.
This supply powers all circuits in the device and must be capable of delivering 6 mA dc plus the transient power MOSFET gate charging current. Input ac voltage sense: For normal operation, connect this pin to a voltage divider across the rectified input power mains. When the voltage on VINAC remains below the brownout threshold for more than I the brownout filter time, the device enters a brownout mode and both output drives are disabled.
Select the input voltage divider ratio for the desired brownout threshold. Select the divider impedance for the desired brownout hysteresis. Voltage reference output: Connect a 0. F ceramic bypass capacitor from this pin to AGND. This 6 VDC reference can be used to bias other circuits requiring less than 2 mA of total supply current.
Output dc voltage sense: Connect this pin to a voltage divider across the output of the power converter. The error amplifier reference voltage is 6 V. Select the output voltage divider ratio for the desired output voltage. Connect the ground side of this divider to ground through a separate short trace I for best output regulation accuracy and noise immunity.
Zero current detection inputs: These inputs expect to see a negative edge when the inductor current I in the respective phases go to zero. The inputs are clamped at 0 V and 3 V. Connect these pins through a current limiting resistor to the zero crossing detection windings of the appropriate boost inductor.
The inductor winding must be connected so that this voltage drops when inductor current decays to zero. When the inductor current drops to zero, the ZCD input must drop below the falling I threshold, approximately 1 V, to cause the gate drive output to rise. The boost PWM power converters ramp current in the boost inductors for a time period proportional to the voltage on the error amplifier output. Once the inductor current decays to 0, the power converter starts another cycle.
TON L 1 The average line current is exactly equal to half of the peak line current, as shown in Equation 2. TON 2? L 2 With TON and L being essentially constant during an ac line period, the resulting triangular current waveform during each switching cycle has an average value proportional to the instantaneous value of the rectified ac line voltage.
This architecture results in a resistive input impedance characteristic at the line frequency and a near-unity power factor. This design reduces ripple current at the input and output, allowing the reduction in size and cost of input and output filters. Optimal phase balance occurs if the individual power stages and the on-times are well-matched.
Mismatches in inductor values do not affect the phase relationship. To provide smooth transition between two-phase and single-phase operation, KT increases by a factor of two in single-phase mode:? This value, less the mV modulator offset, limits on-time to Equation 4. The switching frequency of each phase is limited by minimum period timers. If the current decays to 0 before the minimum period timer elapses, turn-on is delayed, resulting in discontinuous phase current.
The restart timer ensures starting under all circumstances by restarting both phases if either phase ZCD input has not transitioned high-to-low for approximately ? To prevent the circuit from operating in continuous conduction mode CCM , the restart time does not trigger turn-on until both phase currents return to 0. The phase control function differentially modulates the on-times of the A and B channels based on the phase and frequency relationship.
As a result, the current sharing of the A and B channels are proportional to the inductor tolerance. The best current sharing is achieved when both inductors are exactly the same value.
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